The present invention relates to a semiconductor device and method of forming such device, and particularly to a technique which is effectively applicable to a thin package of a large scale integrated circuit having a high integration density.
With an increase in the integration density of semiconductor devices, semiconductor chip sizes now tend to become larger. In view of this point, there has been proposed such a lead-on-chip (LOC) type resin-molded package as disclosed in Japanese Patent Laid-Open No. 241959/86 (corresponding to U.S. Pat. No. 4,862,245). According to this proposal, the semiconductor device has a plurality of inner leads for signals bonded (using an adhesive) onto a circuit-forming surface of a semiconductor chip, through the semiconductor chip and an insulating film. The inner leads for signals, and bonding pads, disposed centrally on the semiconductor chip, are electrically connected with each other through bonding wires and sealed with a molding resin, and a common inner lead (a bus bar inner lead) is provided between the bonding pads and the inner leads for signals, in the vicinity of a longitudinal central line of the circuit-forming surface of the semiconductor chip.